Welcome to my website! I am Yuanlong (Alex) Xiao, A Staff Research Scientist at RapidStream Design Automation Inc. Specialized in accelerating FPGA compilation with Partial Reconfiguration (PR), implementing Network-on-a-Chip (NoC) and AXI-based accelerators on FPGAs in SystemVerilog, and customizing application accelerators in high-level-synthesis (HLS) C++.

Past Research

I finished my Ph.D dissertation in Electrical and System Engineering with Prof. André DeHon at the University of Pennsylvania. I received my M.S in Microelectronics advised by Prof. Jinmei Lai from State Key Laboratory of ASIC & System, Fudan University, where I mainly focused on FPGA silicon layout design, and my B.E in Microelectronics from Sun Yat-sen University.

News

May-10-2023: Very excited to join RapidStream-DA Inc.!

Mar-20-2023: Finally finished my Ph.D Dissertation. Thanks my advisor André!