CV

Education

• B.S. in Microelectronics, Sun Yat-sen University, 2014
• M.S. in Microelectronics, Fudan University, 2017
• Ph.D in Electrical and System Engnieering, University of Pennsylvania, 2022 (expected)

Skills

• Programming
  • Verilog/System Verilog
  • C++
  • Python
  • TCL
  • Bash
  • Matlab
• Platform
  • Xilinx zcu102, Alveo U50, Ultra96
  • Google Cloud Platform
• Tools
  • Vitis
  • RISC-V Toolchain
  • Cadence Virtuoso

Publications

A universal automatic on-chip measurement of FPGA’s internal setup and hold times

FPGA Compile Time with Separate Compilation for FPGA Building Blocks

Fast linking of separately-compiled FPGA blocks without a NoC

HLS-Compatible, Embedded-Processor Stream Links

HiPR: Fast Incremental Custom Partial Reconfiguration for HLS Developers

PLD: Fast FPGA Compilation to Make Reconfigurable Acceleration Compatible with Modern Incremental Refinement Software Development

HiPR: High-level Partial Reconfiguration for Fast Incremental FPGA Compilation

Accelerating FPGA Developments from C to Bitstreams by Partial Reconfiguration

Talks

Fast linking of separately-compiled FPGA blocks without a NoC

December 09, 2020

Conference proceedings talk at 2020 International Conference on Field-Programmable Technology (ICFPT), Maui Hi, USA

HLS-Compatible, Embedded-Processor Stream Links

May 09, 2021

Conference proceedings talk at 2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), New York, USA

Teaching

Teaching Assistant for ESE532

Teaching Assistant for ESE570

Service and leadership

• Currently PhD candidate at the University of Pennsylvania