HiPR: High-level Partial Reconfiguration for Fast Incremental FPGA Compilation
Published in 32nd International Conference on Field Programmable Logic and Applications hosted by Queens University Belfast, United Kingdom. (FPL ’22), 2022
Partial Reconfiguration (PR) is a key technique in the design of modern FPGAs. However, current PR tools heavily rely on the developers to manually conduct PR module definition, floorplanning, and flow control at a low level. The existing PR tools do not consider High-Level-Synthesis languages either, which is of great interest to software developers. We propose HiPR, an open-source framework, to bridge the gap between HLS and PR. HiPR allows the developer to define partially reconfigurable C/C++ functions instead of Verilog modules, which benefits the FPGA incremental compilation and automates the flow from C/C++ to bitstreams. By mapping Rosetta HLS benchmarks, the incremental compilation can be accelerated by 3–10× compared with Xilinx Vitis normal flow without performance loss.
Author’s local PDF copy of paper
Recommended citation: Yuanlong Xiao, Aditya Hota, Dongjoon Park, and André DeHon. “HiPR: High-level Partial Reconfiguration for Fast Incremental FPGA Compilation” Proceedings of the 32nd International Conference on Field Programmable Logic and Applications hosted by Queens University Belfast, United Kingdom. (FPL ’22). 1(1).