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PLD: Make FPGA Compatible with Modern Incremental Refinement Software Development

1 minute read

Published: May 01, 2021

Publications

[1] pld_asplos2022
[2] hlink_fccm2021

PRflow: Reducing FPGA compile time with separate compilation for FPGA building blocks

1 minute read

Published: July 01, 2019

To achieve computation automation in electrical and computer engineering, we write program code as a human-handleable language for tasks like matrix multiplication and linear algebra transformations. The process of converting this code into a computer-executable format or a format used by semiconductor manufacturers to produce chips is known as software or hardware compilation. The performance of hardware implementation can excel software implementation by 10-1000 times. However, the hardware compilation process is lengthy and may take hours to days.

Physical Design and Testing Automation for Reconfigurable chip

2 minute read

Published: September 01, 2015

In semiconductor manufacturing, achieving high performance and low power consumption for FPGA chips requires electrical engineers to diligently handcraft the shapes of all transistors, ensuring the production of efficient integrated circuits. Due to its dominance in FPGA area and delay, the interconnect circuit is traditionally designed and optimized in fully customized fashion, which can be extremely time-consuming. Additionally, the characteristic parameters of chips may vary due to manufacturing variances. As a result, we require a lightweight and cost-effective self-test circuit to obtain these parameters.

publications

A universal automatic on-chip measurement of FPGA’s internal setup and hold times

Published in IEICE Electronics Express 13 (23), 2016

This paper focuses on testing the setup/hold times of the internal elements in FPGAs using only the existing on-chip resources

FPGA Compile Time with Separate Compilation for FPGA Building Blocks

Published in 2019 International Conference on Field-Programmable Technology (ICFPT), 2019

This paper introduces the FPGA compile separation, which allows both incremental compilation and parallel compilation

Fast linking of separately-compiled FPGA blocks without a NoC

Published in 2020 International Conference on Field-Programmable Technology (ICFPT), 2020

This paper introduces the FPGA compile separation which allows connecting modules without NoC.

HLS-Compatible, Embedded-Processor Stream Links

Published in 2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2021

This paper introduces a HLS-streams mapping strategy for small chunk of data transfer between CPU and FPGA Fabrics.

HiPR: Fast Incremental Custom Partial Reconfiguration for HLS Developers

Published in The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2022

This paper proposes the idea of defining partial reconfigurable regions at C-level instead of Verilog-level.

PLD: Fast FPGA Compilation to Make Reconfigurable Acceleration Compatible with Modern Incremental Refinement Software Development

Published in Proceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS ’22), 2022

This paper is about accelerating FPGA compilation, and making it compatible with modern software incremental refinement.

HiPR: High-level Partial Reconfiguration for Fast Incremental FPGA Compilation

Published in 32nd International Conference on Field Programmable Logic and Applications hosted by Queens University Belfast, United Kingdom. (FPL ’22), 2022

This paper is about accelerating FPGA compilation by bridging the gap between High-level Synthesis and Partial Reconfiguration.