Accelerating FPGA Developments from C to Bitstreams by Partial Reconfiguration
Published in Ph.D. Dissertation, 2023
This is my Ph.D dissertation.
Publications
HiPR: High-level Partial Reconfiguration for Fast Incremental FPGA Compilation
Published in 32nd International Conference on Field Programmable Logic and Applications hosted by Queens University Belfast, United Kingdom. (FPL ’22), 2022
This paper is about accelerating FPGA compilation by bridging the gap between High-level Synthesis and Partial Reconfiguration.
PLD: Fast FPGA Compilation to Make Reconfigurable Acceleration Compatible with Modern Incremental Refinement Software Development
Published in Proceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS ’22), 2022
This paper is about accelerating FPGA compilation, and making it compatible with modern software incremental refinement.
HiPR: Fast Incremental Custom Partial Reconfiguration for HLS Developers
Published in The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2022
This paper proposes the idea of defining partial reconfigurable regions at C-level instead of Verilog-level.
HLS-Compatible, Embedded-Processor Stream Links
Published in 2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2021
This paper introduces a HLS-streams mapping strategy for small chunk of data transfer between CPU and FPGA Fabrics.
Fast linking of separately-compiled FPGA blocks without a NoC
Published in 2020 International Conference on Field-Programmable Technology (ICFPT), 2020
This paper introduces the FPGA compile separation which allows connecting modules without NoC.
FPGA Compile Time with Separate Compilation for FPGA Building Blocks
Published in 2019 International Conference on Field-Programmable Technology (ICFPT), 2019
This paper introduces the FPGA compile separation, which allows both incremental compilation and parallel compilation
A universal automatic on-chip measurement of FPGA’s internal setup and hold times
Published in IEICE Electronics Express 13 (23), 2016
This paper focuses on testing the setup/hold times of the internal elements in FPGAs using only the existing on-chip resources