In semiconductor manufacturing, achieving high performance and low power consumption for FPGA chips requires electrical engineers to diligently handcraft the shapes of all transistors, ensuring the production of efficient integrated circuits. Due to its dominance in FPGA area and delay, the interconnect circuit is traditionally designed and optimized in fully customized fashion, which can be extremely time-consuming. Additionally, the characteristic parameters of chips may vary due to manufacturing variances. As a result, we require a lightweight and cost-effective self-test circuit to obtain these parameters.

To automate this time-consuming and error-prone process, I propose an automated transistor transistor-level sizing optimization method for the widely used General Routing Matrix FPGA interconnect circuits. My proposal introduces an area model that incorporates commonly employed engineering practices, including diffusion sharing, transistor folding, and input sharing techniques. By integrating these methods, the model achieves precise area prediction, ensuring accuracy in semiconductor design. To predict the signal transmission delay, I proposed an accurate and effective non-linear delay model that treats the wire within a circuit and the wire between interconnect circuits separately. I developed Python code to automate the entire design process, optimizing program execution by leveraging multiple CPU cores within a workstation. To accelerate the simulation, I prioritized Minimum-Delay as the primary criterion. The global optimization cost is then evaluated by multiplying the interconnect circuit area with the representative path delay, as per our proposed models. The cost reduces 10.9%, when we use 65nm CMOS process chip for evaluation. By employing 10 and 50 threads, the simulation time for various transistor sizing combinations is remarkably improved, achieving a speedup of 9x and 15x, respectively, compared to using a single thread. Compared with the manual design method, our proposed optimization approach explores a larger design space and reduces the optimization time from months to hours. In comparison to the manual design method, our proposed optimization approach explores a significantly larger design space and reduces the optimization time from months to mere hours. To automate the post-manufacture test process, I proposed a low-lost on-chip testing scheme for modern FPGA chips. By using the existing elements on the chip, I can achieve a resolution of 13 ps for commercial chips.

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