PLD: Make FPGA Compatible with Modern Incremental Refinement Software Development
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[1] pld_asplos2022
[2] hlink_fccm2021
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PRflow: Reducing FPGA compile time with separate compilation for FPGA building blocks
Published:
To achieve computation automation in electrical and computer engineering, we write program code as a human-handleable language for tasks like matrix multiplication and linear algebra transformations. The process of converting this code into a computer-executable format or a format used by semiconductor manufacturers to produce chips is known as software or hardware compilation. The performance of hardware implementation can excel software implementation by 10-1000 times. However, the hardware compilation process is lengthy and may take hours to days.
Physical Design and Testing Automation for Reconfigurable chip
Published:
In semiconductor manufacturing, achieving high performance and low power consumption for FPGA chips requires electrical engineers to diligently handcraft the shapes of all transistors, ensuring the production of efficient integrated circuits. Due to its dominance in FPGA area and delay, the interconnect circuit is traditionally designed and optimized in fully customized fashion, which can be extremely time-consuming. Additionally, the characteristic parameters of chips may vary due to manufacturing variances. As a result, we require a lightweight and cost-effective self-test circuit to obtain these parameters.
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PLD: Make FPGA Compatible with Modern Incremental Refinement Software Development
Published:
Publications
[1] pld_asplos2022
[2] hlink_fccm2021
PRflow: Reducing FPGA compile time with separate compilation for FPGA building blocks
Published:
To achieve computation automation in electrical and computer engineering, we write program code as a human-handleable language for tasks like matrix multiplication and linear algebra transformations. The process of converting this code into a computer-executable format or a format used by semiconductor manufacturers to produce chips is known as software or hardware compilation. The performance of hardware implementation can excel software implementation by 10-1000 times. However, the hardware compilation process is lengthy and may take hours to days.
Physical Design and Testing Automation for Reconfigurable chip
Published:
In semiconductor manufacturing, achieving high performance and low power consumption for FPGA chips requires electrical engineers to diligently handcraft the shapes of all transistors, ensuring the production of efficient integrated circuits. Due to its dominance in FPGA area and delay, the interconnect circuit is traditionally designed and optimized in fully customized fashion, which can be extremely time-consuming. Additionally, the characteristic parameters of chips may vary due to manufacturing variances. As a result, we require a lightweight and cost-effective self-test circuit to obtain these parameters.
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PLD: Make FPGA Compatible with Modern Incremental Refinement Software Development
Published:
Publications
[1] pld_asplos2022
[2] hlink_fccm2021
PRflow: Reducing FPGA compile time with separate compilation for FPGA building blocks
Published:
To achieve computation automation in electrical and computer engineering, we write program code as a human-handleable language for tasks like matrix multiplication and linear algebra transformations. The process of converting this code into a computer-executable format or a format used by semiconductor manufacturers to produce chips is known as software or hardware compilation. The performance of hardware implementation can excel software implementation by 10-1000 times. However, the hardware compilation process is lengthy and may take hours to days.
Physical Design and Testing Automation for Reconfigurable chip
Published:
In semiconductor manufacturing, achieving high performance and low power consumption for FPGA chips requires electrical engineers to diligently handcraft the shapes of all transistors, ensuring the production of efficient integrated circuits. Due to its dominance in FPGA area and delay, the interconnect circuit is traditionally designed and optimized in fully customized fashion, which can be extremely time-consuming. Additionally, the characteristic parameters of chips may vary due to manufacturing variances. As a result, we require a lightweight and cost-effective self-test circuit to obtain these parameters.